1. Field of the Invention
The invention relates to a lead frame and a method of fabricating a semiconductor device including the same.
2. Description of the Related Art
As a semiconductor integrated circuit, in particular, a dynamic random access memory (DRAM) has been integrated higher and higher, a semiconductor device is packaged predominantly in a lead-on-chip structure (hereinafter, referred to simply as "LOC structure").
LOC structure is used in place of a chip-on-lead structure, so-called COL structure, which has been used for packaging a semiconductor device including a lead frame having an opening in the vicinity of a center, a hanging lead bridging over the lead frame in a length-wise direction thereof, and an island on which LSI chip is to be mounted.
In order to accomplish higher integration in a semiconductor device, it would be unavoidable for LSI chip to have a greater size, because LSI chip is small in size relative to a semiconductor device, and further because there are standards for the number of pins to be fabricated in a semiconductor device and a pitch between adjacent pins. An increase in size causes an upper limit in integration in a semiconductor device. The above-mentioned COL structure has been developed in order to overcome this problem.
FIG. 1 is a plan view of a semiconductor device having the above-mentioned LOC structure.
As illustrated in FIG. 1, a semiconductor device 1 having a LOC structure is comprised of a lead frame 50 and a semiconductor chip 2 both covered with a resin package 10.
The lead frame 50 is comprised of a plurality of inner leads 51, a plurality of outer leads 52 each connected to an associated inner lead 51, and tie bars 53 connecting outermost outer leads 52 to each other. The tie bar 53 acts as a barrier for stopping resin flow in a later mentioned step of sealing a semiconductor device with resin. The inner leads 51 are located in a length-range of the tie bars 53, and the outer leads 52 are located out of a length-range of the tie bars 53.
The semiconductor chip 2 is electrically connected to the lead frame 50 through the inner leads 51. In order to prevent electrical leakage among the inner leads 51, an electrically insulating adhesive tape 5 are adhered to the semiconductor chip 2 in parallel with and outside electrodes 3 mounted on the semiconductor chip 2. Distal ends 51a of the inner leads 51 are fixed on the adhesive tape 5, and are electrically connected to the electrodes 3 one to one through wires 4.
Hereinbelow is explained a step of sealing a semiconductor device with resin.
In the step of sealing a semiconductor device with resin, as illustrated in FIG. 2, the lead frame 50 fixed on the semiconductor chip 2 with the electrically insulating adhesive tape 5 being sandwiched therebetween is interposed between an upper mold 61 and a lower mold 62.
The upper and lower molds 61 and 62 are formed at surfaces thereof with recesses. The upper and lower molds 61 and 62 are engaged to each other so that the recesses define a cavity 60. The cavity 60 defines an outer shape of a semiconductor package.
The lower mold 62 is formed at a surface thereof with a recess, which defines a gate 63 when the upper and lower molds 61 and 62 are engaged to each other. Resin is introduced into the cavity 60 through the gate 63. The lower mold 62 is formed further with a runner 64 in which resin is pooled, and a pot 65 defining a cylindrical path.
In the step of sealing a semiconductor device with resin, heated resin is introduced first into the pot 65. Resin is then transferred into the runner 64 by means of a plunger (not illustrated) acting as a piston, and thereafter, introduced into the cavity 60 through the gate 63. Thus, the semiconductor chip 2 and the lead frame 50 are sealed with resin.
After the semiconductor chip 2 and the lead frame 50 have been sealed with resin, the tie bars 53 to which the inner leads 51 and the outer leads 52 are connected are cut out to thereby separate the inner leads 51 from one another.
FIG. 14(A) illustrates a lead frame 50C where the tie bars 53 have been cut out. FIG. 14(B) is an enlarged view of an encircled portion in FIG. 14(A).
The tie bar 53 is cut out at hatched regions 53a illustrated in FIG. 14(B) to thereby allow the inner leads 51 and the outer leads 52 to be electrically independent from one another, as illustrated in FIG. 14(A).
Though FIG. 14(A) and FIG. 14(B) illustrate the lead frame 50C in accordance with a later mentioned third embodiment of the present invention, FIG. 14(A) and FIG. 14(B) are used herein for the purpose only of explaining a step of cutting out tie bars. The description with references to FIG. 14 does not mean that FIG. 14(A) and FIG. 14(B) constitutes prior art.
Then, a semiconductor device having been sealed with resin is tested with respect to electrical communication. Test for electrical communication is conducted through the use of a tester illustrated in FIG. 3.
The illustrated tester is comprised of a socket 55 including an upper mold 56 and a lower mold 57. The lower mold 57 is formed at a surface thereof at opposite ends with recesses for exposing the outer leads 52 outside. Test pins 58 upwardly project from the lower mold 57 towards the upper mold 56 in the recesses so that the test pins 58 make contact with the outer leads 52 by virtue of resiliency of the outer leads 52.
The lead frame 50 already having experienced the step of cutting out the tie bars 53 is interposed between the upper mold 56 and the lower mold 57. When the upper and lower molds 56 and 57 are engaged to each other, the recesses formed with the lower mold 57 define a space between the upper and lower molds 56 and 57. The outer leads 52 are exposed to the space, and are electrically tested by means of the test pin 58 to which a testing device (not illustrated) is electrically connected.
Hereinbelow is explained a step of conducting screening inspection.
Screening inspection is conducted after a lead frame of a semiconductor chip 1 having experienced a step of cutting out the tie bars is individually selected, and distal ends of the outer leads 52 are made bent to thereby complete a final product, as illustrated in FIG. 4A. Then, as illustrated in FIG. 4B, the semiconductor chip 1 is mounted on an insulating base 59, and each of the outer leads 52 is electrically tested by means of the test pin 58 to which a testing device (not illustrated) is electrically connected.
A semiconductor chip has been fabricated smaller and smaller in size as technology has developed, and accordingly, the semiconductor chip 1 illustrated in FIG. 1 unavoidably has a space between outermost inner leads 51b. This space causes various problems. For instance, there is produced void in the space because of resin flow in the step of sealing a semiconductor chip with resin. A stress is exerted on the wires 4 due to resin flow, which causes the wires 4 to be deflected when resin is introduced into the cavity 60 illustrated in FIG. 2.
In order to overcome these problems, Japanese Unexamined Patent Publication No. 9-116074 has suggested a lead frame as illustrated in FIG. 5. The illustrated lead frame 50 is designed to have a balancing portion 30 comprised of a plurality of branches 51c inwardly extending from outermost inner leads 51b. The balancing portion 30c controls resin flow.
Japanese Unexamined Patent Publication No. 9-116074 has suggested another lead frame including a pair of outer inner leads which are bent a plurality of times to thereby define the balancing portion 30 for controlling resin flow.
Japanese Unexamined Patent Publication No. 9-116074 has suggested still another lead frame including the balancing portion 30 connected only to the tie bar 53, as illustrated in FIG. 6.
However, the above-mentioned conventional lead frames are accompanied with the following problems.
The lead frame 50 illustrated in FIG. 5 is accompanied with a problem that since the branches 51c extending from the outermost inner leads 51b and constituting the balancing portion 30 are independent from one another, it would be difficult to properly form the lead frame 50, in particular, the inner leads 51.
In addition, the balancing portion 30 is likely to be deformed due to resin flow, which causes a problem that the balancing portion 30 protrudes out of a semiconductor package after carrying out the step of sealing a semiconductor device with resin.
Furthermore, the balancing portion 30 in the lead frame 50 illustrated in FIG. 5 is comprised merely of the branches 51c inwardly extending from the outermost inner leads 51b, a resonance band becomes unavoidably wider in the outermost inner leads 51b generally corresponding to a power source or GND. Hence, the balancing portion 30 might exert harmful influence such as noises on neighboring semiconductor devices.
The lead frame 50 illustrated in FIG. 6 can solve the problem of deformation of the balancing portion 30 to some degree. However, the problem that the balancing portion 30 protrudes out of a semiconductor package due to resin flow in a step of sealing a semiconductor device with resin remains unsolved even by the lead frame 50 illustrated in FIG. 6.